54 lines
1.5 KiB
Systemverilog
54 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int unsigned crc = 32'h1;
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bit a, b;
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int cyc = 0;
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int fails_single = 0;
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int fails_multi = 0;
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// verilog_format: off // verible does not support clocking events inside sequence declarations
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sequence s_single;
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@(posedge clk) a
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endsequence
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sequence s_multi;
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@(posedge clk) (a ##1 b);
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endsequence
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sequence s_unused;
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@(posedge clk) b;
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endsequence
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// verilog_format: on
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ap_single: assert property (s_single) else fails_single = fails_single + 1;
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ap_multi: assert property (s_multi) else fails_multi = fails_multi + 1;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[30:0], crc[31] ^ crc[21] ^ crc[1] ^ crc[0]};
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a <= crc[0];
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b <= crc[1];
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if (cyc == 40) $finish;
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end
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// Counts read in final (Postponed) to avoid same-timestep races.
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// Concrete Verilator counts; Questa: fails_single=17 fails_multi=17
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final begin
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`checkd(fails_single, 17);
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`checkd(fails_multi, 17);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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