49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc;
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logic rst = 1'b1;
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logic x = 1'b1;
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int issue_fail;
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int pre_fail;
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int post_fail;
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int pre_temporal_fail;
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int post_temporal_fail;
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a_issue: assert property (disable iff(rst !== 1'b0) @(posedge clk) !x)
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else issue_fail++;
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assert property (disable iff (cyc < 5) @(posedge clk) 0)
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else pre_fail++;
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assert property (@(posedge clk) disable iff (cyc < 5) 0)
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else post_fail++;
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assert property (disable iff (cyc < 5) @(posedge clk) 1 ##1 0)
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else pre_temporal_fail++;
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assert property (@(posedge clk) disable iff (cyc < 5) 1 ##1 0)
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else post_temporal_fail++;
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always @(negedge clk) begin
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cyc <= cyc + 1;
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rst <= cyc < 4;
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x <= cyc < 4;
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if (cyc == 12) begin
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if (issue_fail != 0) $stop;
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if (pre_fail != post_fail) $stop;
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if (pre_temporal_fail != post_temporal_fail) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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