54 lines
1.1 KiB
Systemverilog
54 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk
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);
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unsupported_ctl_type unsupported_ctl_type (clk ? 1 : 2);
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endmodule
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module unsupported_ctl_type (
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input int a
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);
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initial begin
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let PassOn = 6;
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let PassOff = 7;
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let FailOn = 8;
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let FailOff = 9;
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let NonvacuousOn = 10;
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let VacuousOff = 11;
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$assertcontrol(PassOn);
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$assertpasson;
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$assertpasson(a);
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$assertpasson(a, t);
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$assertcontrol(PassOff);
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$assertpassoff;
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$assertpassoff(a);
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$assertpassoff(a, t);
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$assertcontrol(FailOn);
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$assertfailon;
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$assertfailon(a);
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$assertfailon(a, t);
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$assertcontrol(FailOff);
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$assertfailoff;
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$assertfailoff(a);
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$assertfailoff(a, t);
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$assertcontrol(NonvacuousOn);
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$assertnonvacuouson;
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$assertnonvacuouson(a);
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$assertnonvacuouson(a, t);
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$assertcontrol(VacuousOff);
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$assertvacuousoff;
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$assertvacuousoff(a);
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$assertvacuousoff(a, t);
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end
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endmodule
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