59 lines
1.4 KiB
Systemverilog
59 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Get parameter from modport interface
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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interface intf #(
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parameter int ITEM_QTY = 1
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);
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logic item;
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modport source(input item);
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endinterface
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module pass_through (
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intf.source in_port,
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output logic [31:0] item_qty
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);
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intf #(
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.ITEM_QTY(in_port.ITEM_QTY)
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) internal_port ();
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if (internal_port.ITEM_QTY == 1) begin : g_saw_default_item_qty
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$error("generate if evaluated internal_port.ITEM_QTY as interface default 1");
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end
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else if (internal_port.ITEM_QTY != 20) begin : g_bad_item_qty
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$error("generate if evaluated internal_port.ITEM_QTY as neither 1 nor 20");
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end
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assign internal_port.item = in_port.item;
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assign item_qty = internal_port.ITEM_QTY + internal_port.item;
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endmodule
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module t;
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intf #(
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.ITEM_QTY(20)
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) in_port ();
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logic [31:0] item_qty;
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assign in_port.item = 1'b0;
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pass_through dut (
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.in_port (in_port),
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.item_qty(item_qty)
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);
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initial begin
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`checkd(item_qty, 20);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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