46 lines
924 B
Systemverilog
Executable File
46 lines
924 B
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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module t_randomize_module_var;
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int golden_queue[$];
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class Cls;
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rand bit deq;
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constraint valid_enq {
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if (golden_queue.size() == 0) {
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deq == 0;
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}
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}
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endclass
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Cls tr;
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initial begin
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tr = new;
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// Test 1: Empty queue - deq must be 0
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if (tr.randomize() == 0) begin
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$stop;
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end
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if (tr.deq != 0) begin
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$display("Error: Expected deq=0 when queue is empty, got %0d", tr.deq);
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$stop;
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end
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// Test 2: Non-empty queue - deq can be 0 or 1
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golden_queue.push_back(42);
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if (tr.randomize() == 0) begin
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$stop;
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end
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// deq can be 0 or 1, both are valid
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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