35 lines
657 B
Systemverilog
35 lines
657 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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class object_registry #(
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type T = int
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);
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endclass
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class packer;
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typedef object_registry#(packer) type_id;
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endclass
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endpackage
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package c_pkg;
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import pkg::*;
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class compat_packer extends pkg::packer;
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typedef object_registry#(c_pkg::compat_packer) type_id;
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endclass
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endpackage
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import pkg::*;
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import c_pkg::*;
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module t;
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initial begin
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compat_packer c;
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c = new();
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$finish;
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end
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endmodule
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