28 lines
575 B
Systemverilog
28 lines
575 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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wire mem_wire;
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bit [15:0] idx = 65535;
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bit mem_reg[0:34000];
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assign mem_wire = mem_reg[idx];
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always @(posedge clk) begin
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if (idx < 65533) begin
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$display("oob_val %d", mem_wire);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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idx <= idx - 1;
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mem_reg[idx] <= 0;
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end
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end
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endmodule
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