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99 lines
3.3 KiB
Systemverilog
99 lines
3.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while (0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc = 0;
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covergroup cg_binsof with function sample (bit [6:0] a, bit b, bit enabled);
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cp_a: coverpoint a {
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ignore_bins ignored = {7};
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bins low = {[0 : 1]};
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bins high = {2};
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bins arrayed[] = {3, 4};
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bins rest = default;
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}
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cp_b: coverpoint b {bins low = {0}; bins high = {1}; bins either = {[0 : 1]};}
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// Overlapping coverpoint bins must not count a selected cross bin twice.
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all_products: cross cp_a, cp_b{
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bins combined = binsof (cp_a);
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}
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named: cross cp_a, cp_b{bins selected = binsof (cp_a.low);}
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other_axis: cross cp_a, cp_b{bins selected = (binsof (cp_b.low));}
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array_bins: cross cp_a, cp_b{bins selected = binsof (cp_a.arrayed);}
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overlapping: cross cp_a, cp_b{
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bins lhs = binsof (cp_a.low);
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bins rhs = binsof (cp_b.low);
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}
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guarded: cross cp_a, cp_b iff (enabled) {
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bins selected = binsof (cp_a.low) iff (a == 0);
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bins selected_one = binsof (cp_a.low) iff (a == 1);
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}
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// Non-normal coverpoint bins do not contribute any cross products.
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empty_selection: cross cp_a, cp_b{
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bins ignored = binsof (cp_a.ignored);
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bins defaulted = binsof (cp_a.rest);
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}
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endgroup
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covergroup cg_auto with function sample (bit a, bit b);
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coverpoint a;
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coverpoint b;
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all_products: cross a, b{bins combined = binsof (a);}
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endgroup
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covergroup cg_transition with function sample (bit [6:0] a, bit b);
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cp_a: coverpoint a {bins seq = (0 => 1); bins two = {2};}
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cp_b: coverpoint b;
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transitions: cross cp_a, cp_b{bins selected = binsof (cp_a.seq);}
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endgroup
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covergroup cg_empty with function sample (bit a, bit b);
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cp_a: coverpoint a {ignore_bins ignored = {0, 1};}
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cp_b: coverpoint b;
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empty_product: cross cp_a, cp_b{bins selected = binsof (cp_b);}
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endgroup
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cg_binsof cov = new;
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cg_auto auto_cov = new;
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cg_transition trans_cov = new;
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cg_empty empty_cov = new;
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always @(posedge clk) begin
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if (cyc == 0) begin
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`checkr(cov.get_inst_coverage(), 0.0);
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`checkr(auto_cov.get_inst_coverage(), 0.0);
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`checkr(trans_cov.get_inst_coverage(), 0.0);
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`checkr(empty_cov.get_inst_coverage(), 0.0);
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end
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if (cyc < 18) begin
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cov.sample(7'(cyc / 2), 1'(cyc), cyc != 0);
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auto_cov.sample(1'(cyc / 2), 1'(cyc));
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empty_cov.sample(1'(cyc / 2), 1'(cyc));
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if (cyc < 6) trans_cov.sample(7'(cyc % 3), 1'(cyc / 3));
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if (cyc == 0) begin
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`checkr(cov.get_inst_coverage(), 20.0);
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`checkr(auto_cov.get_inst_coverage(), 60.0);
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end
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end
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else begin
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`checkr(cov.get_inst_coverage(), 100.0);
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`checkr(auto_cov.get_inst_coverage(), 100.0);
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`checkr(trans_cov.get_inst_coverage(), 100.0);
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`checkr(empty_cov.get_inst_coverage(), 100.0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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++cyc;
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end
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endmodule
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