Geza Lore c7a262b05d Optimize bit select removal earlier in Dfg (#7762) ...

Add a simple Dfg pass that removes redundant bit selects early. This
can significantly cut down on downstream work and remove some temporary
variables introduced during synthesis.

2026-06-11 16:00:30 +01:00

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t

Optimize bit select removal earlier in Dfg (#7762)

2026-06-11 16:00:30 +01:00

.gdbinit

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.gitignore

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CMakeLists.txt

Remove multi-threaded FST tracing (#7443)

2026-04-19 16:02:12 +01:00

driver.py

Apply 'make format'

2026-06-02 20:47:02 +00:00

input.vc

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input.xsim.vc

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Makefile

Test: Remove old Makefile rules

2026-04-13 21:09:09 -04:00

Makefile_obj

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