verilator/test_regress
Geza Lore 0ee25038ac
Optimize V3Gate inlining heuristic (#7716)
V3Gate used to inline too many expensive operations. One particularly
bad example is inlining `{<<{wide}}` (bit-reverse of a wide signal),
which is a single input node, but is quite expensive to compute, which
we always used to inline.

Change the heuristic to only inline single input nodes if they are not
wide, or a cheap wide operation, otherwise treat them the same as
multi-input ops and inline them only if they are used no more than once.
2026-06-11 20:59:18 +01:00
..
t Optimize V3Gate inlining heuristic (#7716) 2026-06-11 20:59:18 +01:00
.gdbinit
.gitignore
CMakeLists.txt Remove multi-threaded FST tracing (#7443) 2026-04-19 16:02:12 +01:00
Makefile Test: Remove old Makefile rules 2026-04-13 21:09:09 -04:00
Makefile_obj
driver.py Apply 'make format' 2026-06-02 20:47:02 +00:00
input.vc
input.xsim.vc