verilator/test_regress
Geza Lore 0e769d42a1 Optimize trigger evaluation
Pack the elements of VlTriggerVec as dense bits (instead of a 1 byte
bool per bit), and check whether they are set on a word granularity.
This effectively transforms conditions of the form `if (trig.at(0) |
trig.at(2) | trig.at(64))` into `if (trig.word(0) & 0x5 | trig.word(1) &
0x1)`. This improves OpenTitan ST by about 1%, worth more on some other
designs.
2023-04-24 09:09:36 +02:00
..
t Optimize trigger evaluation 2023-04-24 09:09:36 +02:00
.gdbinit
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Fix cmake 3.12+ warnings on MSWIN. 2023-02-03 17:16:39 -05:00
Makefile Copyright year update 2023-01-01 10:18:39 -05:00
Makefile_obj Add CFG_CXXFLAGS_STD so CFG_CXXFLAGS_STD_NEWEST can still exist (#3881) 2023-01-22 09:44:50 -05:00
driver.pl Parse process class, and report runtime errors (#3612) 2023-04-08 15:04:42 -04:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc