13 lines
310 B
Systemverilog
13 lines
310 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class EventClass;
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event e;
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task sleep; @e; endtask
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task wake; ->e; endtask
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endclass
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