20 lines
355 B
Systemverilog
20 lines
355 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire a;
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wire b;
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assign a = b + 1'b1;
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assign b = a + 1'b1;
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endmodule
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