46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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module t;
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sub #(.P(1)) suba ();
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sub #(.P(10)) subb ();
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int v;
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initial begin
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v = suba.f_no_st();
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`checkh(v, 3);
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v = suba.f_no_st();
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`checkh(v, 4);
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v = subb.f_no_st();
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`checkh(v, 'hc);
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v = subb.f_no_st();
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`checkh(v, 'h16);
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v = suba.f_no_st();
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`checkh(v, 5);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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parameter P = 1;
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// verilator lint_off IMPLICITSTATIC
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function int f_no_st();
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// This static is unique within each parameterized module
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static int st = 2;
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st += P;
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return st;
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endfunction
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endmodule
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