27 lines
560 B
Systemverilog
27 lines
560 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Class #(
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parameter WIDTH
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);
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typedef logic [WIDTH-1:0] word;
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typedef struct {word w;} Struct;
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endclass
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module t;
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Class #(1)::Struct s1;
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Class #(1)::Struct s2;
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Class #(2)::Struct s3;
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initial begin
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$display("%p", s1);
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$display("%p", s2);
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$display("%p", s3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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