52 lines
1.3 KiB
Systemverilog
52 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Test case #4: $root absolute hierarchical reference to tristate signal.
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// A submodule reads a tristate signal from the top module via $root.
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module sub_root_reader (
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output logic [7:0] val
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);
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assign val = $root.t.root_bus;
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endmodule
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module t;
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tri [7:0] root_bus;
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logic root_we;
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assign root_bus = root_we ? 8'hCC : 8'hzz;
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logic [7:0] root_readback;
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sub_root_reader u_reader (.val(root_readback));
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initial begin
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#1;
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root_we = 1'b0;
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#1;
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`checkh(root_readback, 8'hzz);
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#1;
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root_we = 1'b1;
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#1;
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`checkh(root_readback, 8'hCC);
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#1;
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root_we = 1'b0;
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#1;
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`checkh(root_readback, 8'hzz);
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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