140 lines
3.7 KiB
Systemverilog
140 lines
3.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`ifdef verilator
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`define no_optimize(v) $c(v)
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`else
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`define no_optimize(v) (v)
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`endif
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// verilog_format: on
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module t (
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input string empty_no_opt
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);
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// Note $sscanf already tested elsewhere
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reg [3:0] n;
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reg [63:0] q;
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reg [16*8:1] wide;
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reg [8:1] ochar;
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reg [48*8:1] str;
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reg [48*8:1] str2;
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string str3;
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reg [39:0] instruction_str[1:0];
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real r;
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function string cvt2string(input int width, input int v);
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string fmt;
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$sformat(fmt, "%0d'h%%%0dh", width, (width - 1) / 4 + 1);
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$sformat(cvt2string, {"FMT=", fmt, empty_no_opt}, v);
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$display("Format '%s' -> '%s'", fmt, cvt2string);
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endfunction
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int mem[2] = '{1, 2};
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string s;
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initial begin
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n = 4'b1100;
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q = 64'h1234_5678_abcd_0123;
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wide = "hello-there12345";
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$sformat(str, "n=%b q=%d w=%s", n, q, wide);
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`checks(str, "n=1100 q= 1311768467750060323 w=hello-there12345");
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q = {q[62:0], 1'b1};
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$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
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`checks(str2, "n=1100 q= 2623536935500120647 w=hello-there12345");
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str3 = $sformatf("n=%b q=%d w=%s", n, q, wide);
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`checks(str3, "n=1100 q= 2623536935500120647 w=hello-there12345");
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$swrite(str2, "e=%e", r);
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$swrite(str2, "e=%f", r);
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$swrite(str2, "e=%g", r);
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str3 = "hello";
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$swrite(str2, {str3, str3});
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`checks(str2, "hellohello");
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r = 0.01;
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$swrite(str2, "e=%e f=%f g=%g", r, r, r);
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`checks(str2, "e=1.000000e-02 f=0.010000 g=0.01");
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$swrite(str2, "mod=%m");
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`checks(str2, "mod=top.t");
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$swrite(str2, "lib=%l");
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`checks(str2, "lib=work.t");
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str3 = $sformatf("u=%u", {"a", "b", "c", "d"}); // Value selected so is printable
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`checks(str3, "u=dcba");
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str3 = $sformatf("v=%v", 4'b01xz); // Value selected so is printable
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`ifdef TEST_VERBOSE
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$display("chkv %s", str3);
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`endif
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str3 = $sformatf("z=%z", {"a", "b", "c", "d"}); // Value selected so is printable
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`ifdef TEST_VERBOSE
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$display("chkz %s", str3);
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`endif
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$sformat(ochar, "%s", "c");
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`checks(ochar, "c");
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$swrite(str2, 4'd12);
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`checks(str2, "12");
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$swriteb(str2, 4'd12);
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`checks(str2, "1100");
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$swriteh(str2, 4'd12);
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`checks(str2, "c");
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$swriteo(str2, 4'd12);
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`checks(str2, "14");
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str3 = "foo";
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$sformat(str3, "%s", str3); // $sformat twice so verilator does not
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$sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo")
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`checks(str3, "foo");
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$sformat(instruction_str[0], "%s", "Hello");
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$sformat(instruction_str[1], "%s", "World");
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`checks(instruction_str[0], "Hello");
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`checks(instruction_str[1], "World");
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s = cvt2string(`no_optimize(2), `no_optimize(2 * 16));
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`checks(s, "FMT=2'h20");
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s = cvt2string(`no_optimize(14), `no_optimize(14 * 16));
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`checks(s, "FMT=14'h00e0");
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s = "hello";
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s = $sformatf({"%x", "-const"}, s);
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`checks(s, "68656c6c6f-const");
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s = "hello";
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s = $sformatf({"%x", empty_no_opt}, s);
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`checks(s, "68656c6c6f"); // Simulators vary in output; hex required by V3Randomize
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// Also is more consistent with when have $sformat("%x", "string-as-verilog-number")
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s = $sformatf("%s", "constified");
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s = $sformatf("%s", s);
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s = $sformatf("%s", s);
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`checks(s, "constified");
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$display(mem); // Implied %p
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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