29 lines
619 B
Systemverilog
29 lines
619 B
Systemverilog
// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package Some_pkg;
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typedef struct packed {int foo;} some_struct_t;
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endpackage
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module sub #(
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parameter Some_pkg::some_struct_t the_some_struct
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) ();
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endmodule
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module t (
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input clk
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);
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// finish report
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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sub #(.the_some_struct(Some_pkg::some_struct_t'{foo: 1})) the_sub ();
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endmodule
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