54 lines
1.0 KiB
Systemverilog
54 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [1:0] in;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [1:0] out10; // From test of Test.v
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wire [1:0] out32; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.out32(out32[1:0]),
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.out10(out10[1:0]),
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// Inputs
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.in(in[1:0])
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);
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// Test loop
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always @(posedge clk) begin
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in <= in + 1;
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`ifdef TEST_VERBOSE
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$write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10);
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`endif
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if (in == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Outputs
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out32,
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out10,
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// Inputs
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in
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);
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input [1:0] in;
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output [1:0] out32;
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output [1:0] out10;
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assign out32 = in[3:2];
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assign out10 = in[1:0];
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endmodule
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