22 lines
428 B
Systemverilog
22 lines
428 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [43:0] mi;
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reg sel;
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reg [3:0] sel2;
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always @(posedge clk) begin
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mi = 44'h123;
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sel = mi[44];
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sel2 = mi[44:41];
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$write("Bad select %x %x\n", sel, sel2);
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end
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endmodule
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