20 lines
373 B
Systemverilog
20 lines
373 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int a = 0;
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function int f(output int a);
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a = 1;
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return a;
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endfunction
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assert property (@(posedge clk) f(a) >= 0);
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endmodule
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