52 lines
1.3 KiB
Systemverilog
52 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test: rand_mode() used as a function argument (not standalone expression)
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// Ensures nested rand_mode() calls inside function arguments are properly
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// transformed and do not cause Internal Error in V3SplitVar.
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class RandModeClass;
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rand int x;
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rand int y;
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constraint c {
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x inside {[1 : 255]};
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y inside {[1 : 255]};
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}
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task check_mode(string name, int actual, int expected);
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if (actual !== expected) begin
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$display("Error: %s.rand_mode() = %0d, expected %0d", name, actual, expected);
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$stop;
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end
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endtask
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// Task that calls check_mode with rand_mode() as argument
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task test_funcarg;
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check_mode("x", x.rand_mode(), 1);
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check_mode("y", y.rand_mode(), 1);
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x.rand_mode(0);
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check_mode("x", x.rand_mode(), 0);
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check_mode("y", y.rand_mode(), 1);
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x.rand_mode(1);
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check_mode("x", x.rand_mode(), 1);
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// Also test using rand_mode() in $display arguments
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$display("x.rand_mode=%0d y.rand_mode=%0d", x.rand_mode(), y.rand_mode());
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endtask
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endclass
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module t;
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initial begin
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automatic RandModeClass obj = new;
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obj.test_funcarg();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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