77 lines
1.9 KiB
Systemverilog
77 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Test: this.randomize() called in derived class with inherited rand members
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// and constraints from base class. Verifies IS_RANDOMIZED propagation and
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// membersel write_var fallback for ancestor classes.
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class sub_cfg_c;
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rand bit enabled;
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constraint defaults {
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soft enabled == 1'b0;
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}
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endclass
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class base_c;
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rand sub_cfg_c cfg;
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rand int unsigned watchdog;
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constraint override_cons {
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cfg.enabled == 1'b1;
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}
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constraint watchdog_range {
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watchdog inside {[32'd50:32'd200]};
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}
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function new();
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cfg = new();
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endfunction
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endclass
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// Derived class: no additional rand members, calls this.randomize()
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class derived_c extends base_c;
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function int do_randomize();
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return this.randomize();
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endfunction
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endclass
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// Deep inheritance: grandchild with no rand members
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class grandchild_c extends derived_c;
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function int do_rand_deep();
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return this.randomize();
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endfunction
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endclass
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module t;
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initial begin
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automatic derived_c d = new();
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automatic grandchild_c g = new();
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// Test derived class this.randomize()
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repeat (20) begin
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`checkd(d.do_randomize(), 1)
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`checkd(d.cfg.enabled, 1)
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`checkd(d.watchdog >= 32'd50 && d.watchdog <= 32'd200, 1)
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end
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// Test deep inheritance this.randomize()
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repeat (20) begin
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`checkd(g.do_rand_deep(), 1)
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`checkd(g.cfg.enabled, 1)
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`checkd(g.watchdog >= 32'd50 && g.watchdog <= 32'd200, 1)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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