60 lines
1.4 KiB
Systemverilog
60 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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initial begin
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int q[$];
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// Basic slice assignment: overwrite middle elements
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q = '{10, 20, 30, 40, 50};
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q[1:3] = '{99, 88, 77};
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`checkh(q[0], 10);
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`checkh(q[1], 99);
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`checkh(q[2], 88);
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`checkh(q[3], 77);
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`checkh(q[4], 50);
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`checkh(q.size, 5);
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// Slice assignment at start
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q = '{10, 20, 30, 40, 50};
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q[0:1] = '{11, 22};
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`checkh(q[0], 11);
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`checkh(q[1], 22);
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`checkh(q[2], 30);
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`checkh(q[3], 40);
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`checkh(q[4], 50);
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// Slice assignment at end
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q = '{10, 20, 30, 40, 50};
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q[3:4] = '{44, 55};
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`checkh(q[0], 10);
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`checkh(q[1], 20);
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`checkh(q[2], 30);
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`checkh(q[3], 44);
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`checkh(q[4], 55);
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// Single-element slice
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q = '{10, 20, 30, 40, 50};
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q[2:2] = '{66};
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`checkh(q[0], 10);
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`checkh(q[1], 20);
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`checkh(q[2], 66);
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`checkh(q[3], 40);
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`checkh(q[4], 50);
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// Verify size unchanged after all operations
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`checkh(q.size, 5);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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