50 lines
899 B
Systemverilog
50 lines
899 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug477
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module t (
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input rst_n,
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input clk,
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output out
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);
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submod #(.STAGES(5)) u2 (.*);
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endmodule
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module submod ( /*AUTOARG*/
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// Outputs
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out,
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// Inputs
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rst_n,
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clk
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);
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parameter STAGES = 4;
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input rst_n;
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input clk;
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output out;
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reg [STAGES-1:0] r_rst;
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generate
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// for i=0..5 (5+1-1)
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for (genvar i = 0; i < STAGES + 1 - 1; i = i + 1) begin
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n) r_rst[i] <= 1'b0;
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else begin
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if (i == 0) r_rst[i] <= 1'b1;
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else r_rst[i] <= r_rst[i-1]; // i=0, so -1 wraps to 7
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end
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end
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end
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endgenerate
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wire out = r_rst[STAGES-1];
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endmodule
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