38 lines
764 B
Systemverilog
38 lines
764 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function integer max2;
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input integer x;
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input integer y;
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begin
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begin : blk
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automatic int temp;
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temp = x;
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end
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end
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max2 = (x > y) ? x : y;
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endfunction
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function integer max4;
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input integer x;
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input integer y;
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input integer z;
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input integer w;
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// MAX2 is used multiple times
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max4 = max2(max2(x, y), max2(z, w));
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endfunction
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localparam MAX4 = max4(1, 1, 0, 0);
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initial begin
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if (MAX4 != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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