57 lines
1.0 KiB
Systemverilog
57 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug511
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module t (
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input clk
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);
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wire [7:0] au;
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wire [7:0] as;
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Test1 test1 (.au);
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Test2 test2 (.as);
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] result=%x %x\n", $time, au, as);
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`endif
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if (au != 'h12) $stop;
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if (as != 'h02) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Test1 (
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output [7:0] au
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);
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wire [7:0] b;
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wire signed [3:0] c;
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// verilator lint_off WIDTH
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assign c = -1; // 'hf
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assign b = 3; // 'h3
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assign au = b + c; // 'h12
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// verilator lint_on WIDTH
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endmodule
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module Test2 (
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output [7:0] as
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);
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wire signed [7:0] b;
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wire signed [3:0] c;
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// verilator lint_off WIDTH
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assign c = -1; // 'hf
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assign b = 3; // 'h3
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assign as = b + c; // 'h12
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// verilator lint_on WIDTH
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endmodule
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