75 lines
1.5 KiB
Systemverilog
75 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: CC0-1.0
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`ifdef PROCESS_TOP
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// verilog_format: off
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`define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2__under != (in0 & in1)) begin \
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$display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2__under); \
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$stop; \
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end
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// verilog_format: on
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic in0, in1;
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logic out0, out1, out2__under;
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logic [31:0] count = 0;
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// actually XOR and OR and AND
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secret i_secret (
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.in0(in0),
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.in1(in1),
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.out0(out0),
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.out1(out1),
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.out2__under(out2__under)
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);
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always @(posedge clk) begin
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count <= count + 32'd1;
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if (count == 32'd1) begin
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in0 <= 1'b0;
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in1 <= 1'b0;
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end
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else if (count == 32'd2) begin
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`CHECK
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in0 <= 1'b1;
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in1 <= 1'b0;
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end
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else if (count == 32'd3) begin
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`CHECK
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in0 <= 1'b0;
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in1 <= 1'b1;
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end
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else if (count == 32'd4) begin
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`CHECK
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in0 <= 1'b1;
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in1 <= 1'b1;
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end
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else if (count == 32'd5) begin
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`CHECK
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`else
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module secret (
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input in0,
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input in1,
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output out0,
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output out1,
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output out2__under
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);
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assign out0 = in0 ^ in1;
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assign out1 = in0 | in1;
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assign out2__under = in0 & in1;
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endmodule
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`endif
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