75 lines
1.6 KiB
Systemverilog
75 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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// bug998
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interface intf #(
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parameter PARAM = 0
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) ();
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/* verilator lint_off MULTIDRIVEN */
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logic val;
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/* verilator lint_on MULTIDRIVEN */
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function integer func();
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return 5;
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endfunction
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endinterface
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module t1 (
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intf mod_intf
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);
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initial begin
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$display("%m %d", mod_intf.val);
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end
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endmodule
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module t;
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intf #(.PARAM(1)) my_intf[1:0] ();
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generate
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genvar the_genvar;
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begin : ia
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for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
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begin
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assign my_intf[the_genvar].val = '1;
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t1 t (.mod_intf(my_intf[the_genvar]));
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end
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end
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end
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endgenerate
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generate
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genvar the_second_genvar;
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begin : ib
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intf #(.PARAM(1)) my_intf[1:0] ();
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for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf
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begin
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assign my_intf[the_second_genvar].val = '1;
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t1 t (.mod_intf(my_intf[the_second_genvar]));
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end
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end
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end
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endgenerate
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generate
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genvar the_third_genvar;
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begin : ic
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for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf
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begin
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intf #(.PARAM(1)) my_intf[1:0] ();
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assign my_intf[the_third_genvar].val = '1;
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t1 t (.mod_intf(my_intf[the_third_genvar]));
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end
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end
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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