61 lines
1.0 KiB
Systemverilog
61 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug998
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interface intf #(
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parameter PARAM = 0
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) ();
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int p1;
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generate
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initial p1 = 1;
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endgenerate
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int p2;
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generate
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begin
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initial p2 = 1;
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end
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endgenerate
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int p3;
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int p3_no;
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if (PARAM == 1) initial p3 = 1;
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else initial p3_no = 1;
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int p4;
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int p4_no;
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case (PARAM)
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1: initial p4 = 1;
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default:
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initial p4_no = 1;
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endcase
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int p5;
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for (genvar g = 0; g <= PARAM; ++g) initial p5 = 1;
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endinterface
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module t (
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input clk
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);
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intf #(.PARAM(1)) my_intf ();
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always @(posedge clk) begin
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if (my_intf.p1 != 1) $stop;
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if (my_intf.p2 != 1) $stop;
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if (my_intf.p3 != 1) $stop;
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if (my_intf.p3_no != 0) $stop;
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if (my_intf.p4 != 1) $stop;
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if (my_intf.p4_no != 0) $stop;
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if (my_intf.p5 != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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