92 lines
1.9 KiB
Systemverilog
92 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008-2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [9:0] I1 = crc[9:0];
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wire [9:0] I2 = crc[19:10];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [9:0] S; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.S(S[9:0]),
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// Inputs
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.I1(I1[9:0]),
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.I2(I2[9:0])
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);
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wire [63:0] result = {32'h0, 22'h0, S};
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`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Outputs
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S,
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// Inputs
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I1,
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I2
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);
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input [9:0] I1 /*verilator public*/;
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input [9:0] I2 /*verilator public*/;
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output reg [9:0] S /*verilator public*/;
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always @(I1 or I2) t2(I1, I2, S);
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task t1;
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input In1, In2;
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output Sum;
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Sum = In1 ^ In2;
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endtask
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task t2;
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input [9:0] In1, In2;
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output [9:0] Sum;
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integer I;
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begin
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for (I = 0; I < 10; I = I + 1) t1(In1[I], In2[I], Sum[I]);
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end
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endtask
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endmodule
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