88 lines
1.4 KiB
Systemverilog
88 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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clk
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);
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input clk;
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reg [2:0] a;
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reg [2:0] b;
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reg q;
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f6 f6 ( /*AUTOINST*/
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// Outputs
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.q(q),
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// Inputs
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.a(a[2:0]),
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.b(b[2:0]),
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.clk(clk)
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);
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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a <= 3'b000;
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b <= 3'b100;
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end
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if (cyc == 2) begin
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a <= 3'b011;
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b <= 3'b001;
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if (q != 1'b0) $stop;
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end
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if (cyc == 3) begin
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a <= 3'b011;
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b <= 3'b011;
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if (q != 1'b0) $stop;
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end
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if (cyc == 9) begin
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if (q != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module f6 (
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a,
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b,
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clk,
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q
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);
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input [2:0] a;
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input [2:0] b;
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input clk;
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output q;
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reg out;
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function func6;
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reg result;
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input [5:0] src;
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begin
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if (src[5:0] == 6'b011011) begin
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result = 1'b1;
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end
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else begin
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result = 1'b0;
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end
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func6 = result;
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end
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endfunction
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wire [5:0] w6 = {a, b};
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always @(posedge clk) begin
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out <= func6(w6);
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end
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assign q = out;
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endmodule
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