86 lines
1.5 KiB
Systemverilog
86 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off WIDTH
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// verilator lint_off VARHIDDEN
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module t (
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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initial crc = 64'h1;
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chk chk (
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.clk(clk),
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.rst_l(1'b1),
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.expr(|crc)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module chk (
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input clk,
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input rst_l,
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input expr
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);
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int errors;
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task printerr;
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input [8*64:1] msg;
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begin
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errors = errors + 1;
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$write("%%Error: %0s\n", msg);
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$stop;
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end
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endtask
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always @(posedge clk) begin
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if (rst_l) begin
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if (expr == 1'b0) begin
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printerr("expr not asserted");
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end
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end
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end
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wire noxs = ((expr ^ expr) == 1'b0);
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// TODO: this test is dodgy, noxs can be proven constant, so this block
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// should never relly trigger...
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reg hasx;
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always @(noxs) begin
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if (noxs) begin
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hasx = 1'b0;
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end
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else begin
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hasx = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst_l) begin
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if (hasx) begin
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printerr("expr has unknowns");
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end
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end
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end
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endmodule
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