38 lines
831 B
Systemverilog
38 lines
831 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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priority_mask,
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// Inputs
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muxed_requests
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);
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parameter ARW = 7;
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// verilator lint_off UNOPTFLAT
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integer i, j;
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output reg [ARW-1:0] priority_mask;
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input [ARW-1:0] muxed_requests;
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always @* begin
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for (i = ARW - 1; i > 0; i = i - 1) begin
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priority_mask[i] = 1'b0;
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// vvvv=== note j=j not j=i; was bug
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for (j = j; j >= 0; j = j - 1) priority_mask[i] = priority_mask[j] | muxed_requests[j];
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end
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//Bit zero is always enabled
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priority_mask[0] = 1'b0;
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end
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endmodule
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// Local Variables:
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// verilog-auto-inst-param-value: t
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// End:
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