78 lines
1.5 KiB
Systemverilog
78 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2006 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer j;
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integer hit_count;
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reg [63:0] cam_lookup_hit_vector;
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strings strings ();
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task show;
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input [8*8-1:0] str;
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reg [7:0] char;
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integer loc;
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begin
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$write("[%0t] ", $time);
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strings.stringStart(8 * 8 - 1);
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for (
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char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)
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) begin
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$write("%c", char);
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end
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$write("\n");
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end
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endtask
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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show("hello\000xx");
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end
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if (cyc == 2) begin
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show("world\000xx");
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end
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if (cyc == 4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module strings;
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// **NOT** reentrant, just a test!
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integer index;
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task stringStart;
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input [31:0] bits;
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begin
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index = (bits - 1) / 8;
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end
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endtask
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function isNull;
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input [7:0] chr;
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isNull = (chr == 8'h0);
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endfunction
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function [7:0] stringByte;
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input [8*8-1:0] str;
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begin
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if (index <= 0) stringByte = 8'h0;
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else stringByte = str[index*8+:8];
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index = index - 1;
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end
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endfunction
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endmodule
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