92 lines
2.3 KiB
Systemverilog
92 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test that signed enum types auto-incrementing through zero are accepted.
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// Previously Verilator falsely rejected these with "illegally wrapped around".
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module t;
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// Case 1: signed enum crossing zero (the original bug)
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typedef enum int {
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CROSS_NEG2 = -2,
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CROSS_NEG1, // -1
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CROSS_ZERO, // 0
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CROSS_POS1 // 1
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} cross_zero_e;
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// Case 2: signed enum starting at zero
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typedef enum int {
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START_ZERO = 0,
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START_ONE, // 1
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START_TWO // 2
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} start_zero_e;
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// Case 3: signed enum all negative
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typedef enum int {
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ALL_NEG3 = -3,
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ALL_NEG2, // -2
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ALL_NEG1 // -1
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} all_neg_e;
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// Case 4: signed enum starting at large negative, crossing zero
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typedef enum logic signed [7:0] {
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WIDE_NEG3 = -8'sd3,
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WIDE_NEG2, // -2
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WIDE_NEG1, // -1
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WIDE_ZERO, // 0
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WIDE_POS1, // 1
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WIDE_POS2 // 2
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} wide_cross_e;
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// Case 5: signed enum single value at zero
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typedef enum int {SINGLE_ZERO = 0} single_zero_e;
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// Case 6: signed enum starting at -1, crossing zero
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typedef enum int {
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FROM_NEG1 = -1,
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FROM_ZERO, // 0
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FROM_POS1 // 1
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} from_neg1_e;
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initial begin
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// Case 1: crossing zero
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if (CROSS_NEG2 !== -2) $stop;
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if (CROSS_NEG1 !== -1) $stop;
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if (CROSS_ZERO !== 0) $stop;
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if (CROSS_POS1 !== 1) $stop;
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// Case 2: starting at zero
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if (START_ZERO !== 0) $stop;
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if (START_ONE !== 1) $stop;
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if (START_TWO !== 2) $stop;
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// Case 3: all negative
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if (ALL_NEG3 !== -3) $stop;
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if (ALL_NEG2 !== -2) $stop;
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if (ALL_NEG1 !== -1) $stop;
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// Case 4: wider signed type crossing zero
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if (WIDE_NEG3 !== -8'sd3) $stop;
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if (WIDE_NEG2 !== -8'sd2) $stop;
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if (WIDE_NEG1 !== -8'sd1) $stop;
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if (WIDE_ZERO !== 8'sd0) $stop;
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if (WIDE_POS1 !== 8'sd1) $stop;
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if (WIDE_POS2 !== 8'sd2) $stop;
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// Case 5: single zero
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if (SINGLE_ZERO !== 0) $stop;
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// Case 6: from -1 crossing zero
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if (FROM_NEG1 !== -1) $stop;
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if (FROM_ZERO !== 0) $stop;
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if (FROM_POS1 !== 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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