26 lines
469 B
Systemverilog
26 lines
469 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Jonathon Donaldson
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// SPDX-License-Identifier: CC0-1.0
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// bug855
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module our;
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typedef enum logic {
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n,
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N
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} T_Flg_N;
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typedef struct packed {T_Flg_N N;} T_PS_Reg;
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T_PS_Reg PS = 1'b1;
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initial begin
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$write("P:%s\n", PS.N.name);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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