61 lines
1.7 KiB
Systemverilog
61 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class uvm_object;
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endclass
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class uvm_typeid_base;
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endclass
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class uvm_typeid #(
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type T = uvm_object
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) extends uvm_typeid_base;
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static uvm_typeid #(T) m_b_inst;
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static function uvm_typeid#(T) get();
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if (m_b_inst == null) begin
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m_b_inst = new;
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end
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return m_b_inst;
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endfunction
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endclass
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class base_cmp extends uvm_object;
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endclass
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class base_oth extends uvm_object;
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endclass
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initial begin
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string sc1, sc2, so;
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// IEEE 1800-2023 21.2.1.1 suggests %d of a class is illegal.
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// Howver UVM tests require %0d print unique identifier of the class.
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// In contrast, %x of a class reference, causes errors on several simulators.
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$display("BASE_CMP: %%p=%p", uvm_typeid#(base_cmp)::get());
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$display("BASE_CMP: %%0d=%0d", uvm_typeid#(base_cmp)::get());
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$display("BASE_OTH: %%p=%p", uvm_typeid#(base_oth)::get());
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$display("BASE_OTH: %%0d=%0d", uvm_typeid#(base_oth)::get());
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sc1 = $sformatf(": %0d", uvm_typeid#(base_cmp)::get());
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sc2 = $sformatf(": %0D", uvm_typeid#(base_cmp)::get());
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so = $sformatf(": %0d", uvm_typeid#(base_oth)::get());
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if (sc1 != sc2) begin
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$display("Expected class-to-%%d strings to be ==\n sc1=%s\n sc2=%s", sc1, sc2);
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$stop;
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end
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// TODO make a unique identifier
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// Complication is runtime of %p vs %d; need to pass both string and object?
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// if (sc1 == so) begin
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// $display("Expected class-to-%%d strings to be !=\n sc1=%s\n so=%s", sc1, so);
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// $stop;
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// end
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$finish;
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end
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endmodule
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