37 lines
740 B
Systemverilog
37 lines
740 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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//TODO sub #(.WIDTH(1)) w1();
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//TODO sub #(.WIDTH(2)) w2();
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//TODO sub #(.WIDTH(3)) w3();
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//TODO sub #(.WIDTH(4)) w4();
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sub #(.WIDTH(5)) w5 ();
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub ();
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parameter WIDTH = 5; // WIDTH >= 5 fails. WIDTH <= 4 passes
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typedef struct packed {logic [WIDTH-1:0] data;} [15:0] w_t;
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class WrReqQ;
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w_t w;
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endclass
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initial begin
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if ($bits(w_t) != WIDTH * 16) $stop;
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end
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endmodule
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