69 lines
1.6 KiB
Systemverilog
69 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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class uvm_coreservice;
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static uvm_coreservice inst;
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function new(string name);
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endfunction
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static function uvm_coreservice get();
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if (inst == null) begin
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inst = new("cs-base");
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end
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return inst;
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endfunction
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virtual function string get_factory();
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return "factory";
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endfunction
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endclass
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class uvm_test;
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string m_name;
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string s0 = {m_name, "0"}; // Before new(); this must get "0" not "name0"
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function new(string name);
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m_name = name;
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endfunction
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endclass
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class test extends uvm_test;
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string s1 = {s0, "1"};
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string s2 = {s1, "2"};
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uvm_coreservice cs = uvm_coreservice::get();
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// Below assumes that the above 'cs' executes first.
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// Most simulators require this ordering, but some allow arbitrary order
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// This would require dataflow analysis, so for now Verilator requires user ordering
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string factory = cs.get_factory();
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function new(string name);
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super.new(name);
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endfunction
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endclass
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initial begin
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test t;
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string s;
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t = new("test");
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`checks(t.s0, "0");
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`checks(t.s1, "01");
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`checks(t.s2, "012");
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s = t.factory;
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`checks(s, "factory");
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$finish;
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end
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endmodule
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