53 lines
1.3 KiB
Systemverilog
53 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// A task argument that defaults to a plain variable must alias that variable,
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// not a copy of it: a write through a 'ref' default must propagate back, and a
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// 'const ref' default must observe later updates to the variable.
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module t;
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int shared = 5;
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logic flag = 0;
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logic done = 0;
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// writable 'ref' default: a write through it must reach 'shared'
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task automatic incr(ref int r = shared);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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r = r + 10;
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endtask
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// 'const ref' default: must observe a later update to 'flag'
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task automatic waitflag(output logic odone, const ref logic r = flag);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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while (!r) #1;
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odone = 1'b1;
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endtask
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initial begin
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incr();
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if (shared !== 15) begin
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$write("%%Error: write through default 'ref' lost (shared=%0d)\n", shared);
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$stop;
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end
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fork
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waitflag(done);
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join_none
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#5;
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flag = 1'b1;
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#5;
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if (done !== 1'b1) begin
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$write("%%Error: default 'const ref' did not observe update\n");
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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