47 lines
986 B
Systemverilog
47 lines
986 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// using public_on causes one to be AstCellInline, and that one has correct scope
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// without this, both are AstCellInline, and both are wrong
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/* verilator public_on */
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module t ( /*AUTOARG*/
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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gen_wrapper top_wrap_1 ();
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gen_wrapper top_wrap_2 ();
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endmodule : t
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module sub;
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reg subsig1;
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endmodule : sub
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module gen_wrapper;
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genvar i;
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generate
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for (i = 0; i < 1; i++) begin : gen_loop
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// This fixes the scope
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// localparam int x = 2;
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sub after_gen_loop ();
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end
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endgenerate
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endmodule
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