27 lines
589 B
Systemverilog
27 lines
589 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Anonymous
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struct packed {
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logic [31:0] val1;
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logic [31:0] val2;
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} struct1;
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struct packed {
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logic [31:0] val3;
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logic [31:0] val4;
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} struct2;
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module t (
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output logic [63:0] s1,
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output logic [63:0] s2
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);
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initial struct1 = 64'h123456789_abcdef0;
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always_comb s1 = struct1;
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initial struct2 = 64'h123456789_abcdef0;
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always_comb s2 = struct2;
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endmodule
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