40 lines
741 B
Systemverilog
40 lines
741 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Alias type check error test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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static int counter = 0;
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task wait_for_nba_region;
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static int nba;
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static int next_nba;
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next_nba++;
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nba <= next_nba;
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@(nba);
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counter++;
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endtask
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class Foo;
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task run_phases();
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repeat (2) begin
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fork
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if ($c(1)) wait_for_nba_region();
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join_none
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end
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endtask
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endclass
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module top;
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initial begin
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static Foo p = new;
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p.run_phases();
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#1;
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if (counter != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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