25 lines
592 B
Systemverilog
25 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int q[$] = '{1, 2, 3};
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bit dyn[] = '{0, 0};
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string sq[] = '{"C", "D"};
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initial begin
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if (!(1 inside {q})) $stop;
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if (4 inside {q}) $stop;
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if (!(4 inside {q, 4})) $stop;
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if (!(0 inside {dyn})) $stop;
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if (1 inside {dyn}) $stop;
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if (!("C" inside {sq})) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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