46 lines
861 B
Systemverilog
46 lines
861 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`define DELAY_INIT_CHECK(foo, bar) \
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assign #1 bar = foo; \
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\
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always @(foo, bar) begin \
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$display("%d foo %x, bar %x", $time, foo, bar); \
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end \
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\
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initial begin \
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#5; \
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if (bar != foo) $stop; \
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#5 foo = ~foo; \
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#5; \
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if (bar != foo) $stop; \
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#5 foo = ~foo; \
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#5; \
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if (bar != foo) $stop; \
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end \
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module t ();
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reg foo1;
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wire bar1;
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initial foo1 = '0;
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`DELAY_INIT_CHECK(foo1, bar1)
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reg foo2 = '0;
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wire bar2;
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`DELAY_INIT_CHECK(foo2, bar2)
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reg foo3 = '0;
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reg bar3 = '1;
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`DELAY_INIT_CHECK(foo3, bar3)
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initial begin
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#30;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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