27 lines
607 B
Systemverilog
27 lines
607 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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function automatic logic is_odd(int value);
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logic odd = value % 2 == 1;
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if (!odd) $error($sformatf("%0d is not odd", value));
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return odd;
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endfunction
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always_ff @(posedge clk) begin
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if (cyc[0] == 1'b0 || is_odd(cyc)) cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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