30 lines
681 B
Systemverilog
30 lines
681 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class base_reg_block;
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function new(string name, int x);
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if (name == x) $finish;
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endfunction
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function string build_coverage(int x);
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return $sformatf("%0d", x);
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endfunction
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endclass
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class spi_reg_block extends base_reg_block;
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function new();
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int x = $random();
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super.new(build_coverage(x), x); // <--- BAD, must be first statement
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endfunction
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endclass
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module t;
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initial begin
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spi_reg_block test = new;
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$finish;
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end
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endmodule
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