60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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logic a, b, c;
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// Sequence without arguments
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sequence seq_ab;
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a && b;
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endsequence
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// Sequence with formal arguments (default input direction)
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sequence seq_check(logic sig1, logic sig2);
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sig1 && sig2;
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endsequence
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// Overlapping implication with sequence ref (no args)
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assert property (@(posedge clk) seq_ab |-> c);
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// Non-overlapping implication
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assert property (@(posedge clk) seq_ab |=> c);
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// Sequence with args, multiple references with different actuals
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assert property (@(posedge clk) seq_check(a, b) |-> c);
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assert property (@(posedge clk) seq_check(b, c) |-> a);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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2, 5: begin
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a <= 1'b1;
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b <= 1'b1;
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c <= 1'b1;
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end
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3, 6: begin
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a <= 1'b0;
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b <= 1'b0;
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c <= 1'b1;
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end // c stays high for |=> check
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default: begin
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a <= 1'b0;
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b <= 1'b0;
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c <= 1'b0;
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end
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endcase
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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