30 lines
774 B
Systemverilog
30 lines
774 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 1'b0;
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always #1 clk = ~clk;
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int idx = 0;
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bit a[0:2] = {1, 1, 1};
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always @(posedge clk) begin
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if (idx == 4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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idx <= idx + 1;
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`checkh(a[idx], idx <= 2 ? 1 : 0);
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end
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end
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endmodule
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